Components of SAP-1 Computer with Block Diagram and Comparison with SAP-2

SAP (Simple As Possible) is a simplified computer architecture designed for educational purposes to help students understand the basic concepts of how a computer works, including fetching, decoding, and executing instructions.

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Block Diagram of SAP-1

The SAP-1 architecture consists of components connected via a common W-bus (8-bit bus). The data flows between components through this single bus controlled by the controller-sequencer.

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Components of SAP-1

• Program Counter (PC): A 4-bit counter that stores the address of the next instruction to be fetched. It counts from 0000 to 1111 (0 to 15).

• Input and MAR (Memory Address Register): A 4-bit register that receives the address from the PC and points to the memory location in RAM.

• RAM (16 × 8): A 16-byte memory that stores both instructions and data. It has 16 locations, each 8 bits wide.

• Instruction Register (IR): An 8-bit register that holds the current instruction. The upper 4 bits represent the opcode and lower 4 bits represent the operand (address).

• Controller-Sequencer: Generates control signals (12 control bits) for all components based on the opcode. It uses a ring counter to produce timing signals (T1 to T6).

• Accumulator (A): An 8-bit register that stores intermediate results of arithmetic operations. It is the main working register.

• Adder/Subtractor: Performs addition and subtraction operations. It takes input from the Accumulator and B register and outputs the result.

• B Register: An 8-bit register that holds the second operand for arithmetic operations.

• Output Register: Stores the final result from the Accumulator and sends it to the binary display.

• W-Bus: An 8-bit common bus that connects all components. Only one component can place data on the bus at a time.

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Differences Between SAP-1 and SAP-2

Feature	SAP-1	SAP-2
Bus Size	8-bit W-bus	16-bit address bus + 8-bit data bus
Instruction Set	5 instructions (LDA, ADD, SUB, OUT, HLT)	Extended set with JMP, JNZ, JZ, CALL, RET, etc.
Flags	No flags	Has Sign flag and Zero flag
Registers	Only A and B registers	Multiple registers (A, B, C and additional registers)
Memory	16 bytes (4-bit address)	64 KB (16-bit address)
Addressing	Only direct addressing	Direct, indirect, and register addressing
I/O Capability	Only binary output display	Input port and output ports (hexadecimal)
Program Counter	4-bit	16-bit
Jump/Branch	Not supported	Conditional and unconditional jumps supported
Subroutines	Not supported	Supported with CALL and RET instructions

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Conclusion

SAP-1 is a basic introductory architecture with limited instructions and memory, designed to teach the fetch-decode-execute cycle. SAP-2 is an enhanced version that introduces flags, more registers, larger memory, and jump/subroutine capabilities, making it closer to real-world microprocessors like the Intel 8085.