StudyNp | BIT First Semester – Model Question for Digital Logic

Tribhuwan University

Institute of Science and Technology

Model

Bachelor Level / First Year / First Semester / Science

Bachelors in Information Technology (BIT103)

(Digital Logic)

Full Marks: 60

Pass Marks: 24

Time: 3 Hours

Candidates are required to give their answers in their own words as for as practicable.

The figures in the margin indicate full marks.

Section A

Long Answers Questions

Attempt any TWO questions.

[2*10=20]

Design the full adder circuit using 3 to 8 decoder and explain the working principle.[10]

Design of Full Adder Circuit Using 3-to-8 Decoder

A Full Adder is a combinational circuit that adds three input bits (A, B, Cin) and produces two outputs: Sum (S) and Carry (Cout). It can be implemented using a 3-to-8 decoder and OR gates.

Working Principle

The key idea is that any combinational circuit can be implemented using a decoder and OR gates. A decoder generates all the minterms of the input variables. We simply OR together the required minterms to get the desired output functions.

Steps:

Write the truth table for the full adder
Identify the minterms for each output (Sum and Carry)
Use a 3-to-8 decoder to generate all 8 minterms (m₀ to m₇)
Connect appropriate minterms to OR gates to produce Sum and Carry outputs

Truth Table of Full Adder

A	B	Cin	Sum (S)	Carry (Cout)
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Boolean Expressions (Sum of Minterms)

From the truth table:

$S(A, B, C_{in}) = \sum m(1, 2, 4, 7)$

$C_{out}(A, B, C_{in}) = \sum m(3, 5, 6, 7)$

Circuit Design (Description)

Components Required:

One 3-to-8 Decoder (with inputs A, B, Cin)
Two OR gates

Connections:

Inputs: A, B, and Cin are connected to the three input lines of the 3-to-8 decoder (A as MSB, Cin as LSB)
Decoder Outputs: The decoder produces 8 output lines (D₀ to D₇), each representing one minterm (m₀ to m₇)
OR Gate 1 (for Sum): Connect decoder outputs D₁, D₂, D₄, and D₇ to a 4-input OR gate → Output is Sum
OR Gate 2 (for Carry): Connect decoder outputs D₃, D₅, D₆, and D₇ to a 4-input OR gate → Output is Cout

Circuit Diagram (Block Level)

Design of Full Adder Circuit Using 3-to-8 Decoder

OR gate for Sum receives: D1, D2, D4, D7
OR gate for Cout receives: D3, D5, D6, D7

Explanation of Working

When inputs A, B, Cin are applied, the decoder activates exactly one of its 8 outputs (the one corresponding to the input combination)
For example, if A=1, B=0, Cin=1 → Decoder activates D₅ (minterm 5)
Since D₅ is connected to the Cout OR gate → Cout = 1, and Sum = 0 (D₅ is not connected to Sum OR gate)
This matches the truth table entry for inputs (1, 0, 1)

Conclusion

A 3-to-8 decoder with two OR gates efficiently implements a full adder. This approach is systematic and can be used to implement any combinational circuit — simply identify the minterms and OR them together. The decoder acts as a minterm generator, making the design straightforward and scalable.

What is JK master slave flip-flop? Design its logic circuit, truth table and explain the working principle.[10]

The term LOGIC GATES is to be transmitted as 12 bytes of data. Each character in the term has an ASCII value. The system uses odd parity and left most bit is used as parity bit. An additional parity byte is also sent after the term. The following bytes have arrived at their destination. a. One of the bytes has an error after transmission. Locate which character contains an error. b. Locate the bit that has been transmitted incorrectly. c. Explain how you have arrived at your conclusion.

\begin{array}{|c|c|c|c|c|c|c|c|c|c|}\hline & \text{letters} & 1 & 2 & 3 & 4 & 5 & 6 & 7 & 8 \\ \hline 1 & L & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 0 \\ 2 & O & 0 & 1 & 0 & 0 & 1 & 1 & 1 & 1 \\ 3 & G & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 \\ 4 & I & 0 & 1 & 0 & 0 & 1 & 0 & 0 & 1 \\ 5 & C & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 1 \\ 6 & \langle \text{space} \rangle & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 \\ 7 & G & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 1 \\ 8 & A & 1 & 1 & 0 & 0 & 0 & \mathbf{1} & 0 & 1 \\ 9 & T & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 0 \\ 10 & E & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 \\ 11 & S & 1 & 1 & 0 & 1 & 0 & 0 & 1 & 1 \\ 12 & \text{Parity byte} & 1 & 1 & 0 & 1 & 0 & 0 & 1 & 0 \\ \hline \end{array}

[10]

Section B

Short Answers Questions

Attempt any Eight questions.

[8*5=40]

Show that the dual of the exclusive-OR is equal to its complement. [5]

Explain with state diagram and excitation table for 3-bit binary counter. [5]

Design a decoder with three input lines but with only six output lines. If the value of the input corresponds to 6 or 7, then all output line should be asserted to signal an error. [5]

What are the special characteristics of IC digital logic family? Explain them in brief. [5]

A logic circuit implements the following Boolean function. F=A'C+AC'D It is found that the required input combination A=C=1 can never occur. Using K-map and proper don't care condition find simpler expression for F and implement it using not gate only. [5]

a) Obtain the 9's and 10's complement of i) 13579 ii) 90090 decimal number. b) Convert 6524275 octal to hexadecimal [5]

10.

Design 8 to 1 Multiplexer using two 4to 1 Multiplexers. [5]

11.

Given is a logic (switching) function F1 in the decimal list sum-of-minterms representation.

F_1(A,B,C,D) = \Sigma(0, 2, 3, 5, 7)

d(A,B,C,D) = \Sigma(8, 10, 13, 15)

[5]

12.

Write short notes on: PLA Write short notes on Triggering of flip-flop [2.5+2.5]